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-- Company: 
-- Engineer: 
-- 
-- Create Date:    14:19:57 09/13/2012 
-- Design Name: 
-- Module Name:    CONTROL_UNIT - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;


-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity CONTROL_UNIT is
	port (
		opcode : in std_logic_vector (5 downto 0);
		RegDst : out std_logic;
		RegWrite : out std_logic;
		ALUsrc : out std_logic;
		ALUop : out std_logic_vector (1 downto 0);
		Branch : out std_logic;
		MemWrite : out std_logic;
		MemToReg : out std_logic;
		Jump	: out std_logic;
		Stall : out std_logic
		);
		
		
end CONTROL_UNIT;

architecture Behavioral of CONTROL_UNIT is
	--component declaration
	
	--signal declaration
	
begin
	decode: process (opcode)
	begin
		if opcode = "100011" then -- Load Word
			RegDst 		<= '0';
			RegWrite 	<= '1';
			ALUsrc 		<= '1';
			ALUop 		<= "00";
			Branch 		<= '0';
			MemWrite 	<= '0';
			MemToReg 	<= '1';
			Jump			<= '0';
			Stall 		<= '1';
		elsif opcode = "101011" then -- Store Word
			RegDst 		<= '0';
			RegWrite 	<= '0';
			ALUsrc 		<= '1';
			ALUop 		<= "00";
			Branch 		<= '0';
			MemWrite 	<= '1';
			MemToReg 	<= '0';
			Jump			<= '0';
			Stall 		<= '1';
		elsif opcode = "000100" then -- Branch Equal
			RegDst 		<= '0';
			RegWrite 	<= '0';
			ALUsrc 		<= '0';
			ALUop 		<= "01";
			Branch 		<= '1';
			MemWrite 	<= '0';
			MemToReg 	<= '0';
			Jump			<= '0';
			Stall			<= '0';
		elsif opcode = "000010" then -- Jump
			RegDst 		<= '0';
			RegWrite 	<= '0';
			ALUsrc 		<= '0';
			ALUop 		<= "00";
			Branch 		<= '0';
			MemWrite 	<= '0';
			MemToReg 	<= '0';
			Jump			<= '1';
			Stall			<= '0';
		elsif opcode = "000000" then -- ALU function
			RegDst 		<= '1';
			RegWrite 	<= '1';
			ALUSrc 		<= '0';
			ALUop 		<= "10";
			Branch 		<= '0';
			MemWrite 	<= '0';
			MemToReg 	<= '0';
			Jump			<= '0';
			Stall			<= '0';
			
		elsif opcode = "001111" then -- LOAD immediate	
			RegDst 		<= '0';
			RegWrite 	<= '1';
			ALUSrc 		<= '1';
			ALUop 		<= "00"; -- add
			Branch 		<= '0';
			MemWrite 	<= '0';
			MemToReg 	<= '0'; -- loader alu result inn i register
			Jump			<= '0';
			Stall			<= '1';		
			
		else -- No Operation
			RegDst 		<= '0';
			RegWrite 	<= '0';
			ALUSrc 		<= '0';
			ALUop 		<= "00";
			Branch 		<= '0';
			MemWrite 	<= '0';
			MemToReg 	<= '0';
			Jump			<= '0';
			Stall			<= '0'; 
		end if;
		
	end process;
	
	

end Behavioral;